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  ace24 a c 32 d two - wire serial eeprom ver 1. 2 1 description the ace24ac32 d series are 32,768bits of serial electrical erasable and programmable read only memory, commonly known as eeprom. they are organized as 4096 words of 8 bits (one byte) each. the devices are fabricated with proprietary advanced cm os process for low power and low voltage applications. these devices are available in standard 8 - lead dip, 8 - lead sop, 8 - lead msop, 8 - lead tssop, 8 - lead u son3*2 - 8 , sot - 23 - 5 , and t so t - 23 - 5 packages. a standard 2 - wire serial interface is used to address all read a nd write functions. our extended v cc range (1.8v to 5.5v) devices enables wide spectrum of applications. features ? low voltage and low power operations: ace24ac32d : v cc = 1.8v to 5.5v ? maximum standby current < 1a ? 32 bytes page write mode. ? partial page wri te operation allowed. ? internally organized: 4,096 8 (32k). ? standard 2 - wire bi - directional serial interface. ? schmitt trigger, filtered inputs for noise protection. ? self - timed write cycle (5ms maximum). ? 800 khz (5v), 400 khz (1.8v, 2.5v, 2.7v) compatibilit y. ? automatic erase before write operation. ? write protect pin for hardware data protection. ? high reliability: typically 1, 000,000 cycles endurance. ? 100 years data retention. ? industrial temperature range ( - 40 to 85 ). ? standard 8 - l ead dip/sop/ msop/tssop/ u son3*2 - 8 /sot - 23 - 5 and t so t - 23 - 5 pb - free packages. absolute maximum ratings industrial operating temperature: - 40 to 85 storage temperature: - 50 to 125 input voltage on any pin relative to ground: - 0.3v to v cc + 0.3v maximum voltage: 8 v esd protection on all pins: >2000v n otice : stresses exceed those listed under absolute maximum rating may cause permanent damage to the device. functional operation of the device at conditions beyond those listed in the specification is not guaranteed. prolonged exposur e to extreme conditions may affect device reliability or functionality.
ace24 a c 32 d two - wire serial eeprom ver 1. 2 2 packaging type sop - 8 tssop - 8 dip - 8 msop - 8 u son3 *2 - 8 sot - 23 - 5 t sot - 23 - 5 pin configurations pin name functions ao - a2 device address inputs sda serial data input / open drain output scl serial clock input wp write protect nc no - connect ordering information ace24ac32d xx + x h pb - free u: tube t : tape and reel fm : sop - 8 tm : tssop - 8 dp : dip - 8 om : msop - 8 u a8: uson3*2* - 8 bn: sot - 23 - 5 bns: tso t - 23 - 5 halogen - free
ace24 a c 32 d two - wire serial eeprom ver 1. 2 3 block diagra m pin descriptions (a) s erial c lock (scl) the rising edge of this scl input is to latch data into the eeprom device while the falling edge of this clock is to clock data out of the eeprom device. (b) d evice / c hip s elect a ddresses (a2, a1, a0) these are the chip select input signals for the serial eeprom devices. typically, these signals are hardwired to either v ih or v il . if left unconnected, they are internally recognized as v il . (c) s erial d ata l ine (sda) sda data line is a bi - directional sig nal for the serial devices. it is an open drain output signal and can be wired - or with other open - drain output devices. (d) w rite p rotect (wp) the ace24ac32d devices have a wp pin to protect the whole eeprom array from programming. programming operations are a llowed if wp pin is left un - connected or input to v il . conversely all programming functions are disabled if wp pin is connected to v ih or v cc . read operations is not affected by the wp pins input level.
ace24 a c 32 d two - wire serial eeprom ver 1. 2 4 memory organization the ace24ac32d devices have 1 28 pages respectively. since each page has 32 bytes, random word addressing to ace24ac32d will require 12 bits data word addresses respectively. device operation (a) s erial c lock a nd d ata t ransitions the sda pin is typically pulled to high by an external resi stor. data is allowed to change only when serial clock scl is at v il . any sda signal transition may interpret as either a start or stop condition as described below. (b) s tart c ondition with scl v ih , a sda transition from high to low is interpreted as a start condition. all valid commands must begin with a start condition. (c) s top c ondition with scl v ih , a sda transition from low to high is interpreted as a stop condition. all valid read or write commands end with a stop condition. the device goes into the stand by mode if it is after a read command. a stop condition after page or byte write command will trigger the chip into the standby mode after the self - timed internal programming finish (see figure 1). (d) a cknowledge the 2 - wire protocol transmits address and data to and from the eeprom in 8 bit words. the eeprom acknowledges the data or address by outputting a "0" after receiving each word. the acknowledge signal occurs on the 9 th serial clock after each word. (e) s tandby m ode the eeprom goes into low power standby mo de after a fresh power up, after receiving a stop bit in read mode, or after completing a self - time internal programming operation. figure 1: timing diagram for s tart and stop conditions
ace24 a c 32 d two - wire serial eeprom ver 1. 2 5 figure 2: timing diagram for output acknowledge device addressi ng the 2 - wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke a valid read or write command. the first four most significant bits of the device address must be 1010, which is common to all serial eeprom devi ces. the next three bits are device address bits. these three device address bits (5 th , 6 th and 7 th ) are to match with the external c hip select/address pin states. if a match is made, the eeprom device outputs an acknowledge signal after the 8 th read/write bit, otherwise the chip will go into standby mode. however, matching may not be needed for some or all device address bits (5 th , 6 th and 7 th ) as noted below. the last or 8th bit is a read/write command bit. if the 8th bit is at v ih then the chip goes into read mode. if a 0 is detected, the device enters programming mode. write operations (a) b yte w rite a write operation requires two 8 - bit data word address following the device address word and acknowledge signal. upon receipt of this address, the eeprom wil l respond with a 0 and then clock in the first 8 - bit data word. following receipt of the 8 - bit data word, the eeprom will again output a 0. the addressing device, such as a microcontroller, mus t terminate the write sequence with a stop condition. at t his time the eeprom enters into an internally - timed write cycle state. all inputs are disabled during this write cycle and the eeprom will not respond until the writing is completed (figure 3).
ace24 a c 32 d two - wire serial eeprom ver 1. 2 6 (b) p age w rite the 32 k eeprom are capable of 32 - byte page wri te. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. the micro controller can transmit up to 31 more data words after the eeprom acknowledges receipt of t he first data word. the eeprom will respond with a 0 after each data word is received. the microcontroller must terminate the page write sequence with a stop condition (see figure 4). the lower five bits of the data word address are internally incremente d following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory pag e row location. if more than 64 data words are transmitted to the eeprom, the data word address will roll over and the previous data will be overwritten. (c) a cknowledge p olling acknowledge polling may be used to poll the programming status during a self - timed internal programming. by issuing a valid read or write address command, the eeprom will not acknowledge at the 9th clock cycle if t he device is still in the self - timed programming mode. however, if the programming completes and the chip has returned to the standby mode, the device will return a valid acknowledge signal at the 9 th clock cycle. read operations the read command is simil ar to the write command except the 8 th read/write bit in address word is set to 1. the three read operation modes are described as follows: (a) c urrent a ddress r ead the eeprom internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. to initiate a current address read operation, the micro - controller issues a start bit and a valid device address word with the read/write bit (8 th ) set to 1. the eeprom will response with an acknowle dge signal on the 9 th serial clock cycle. an 8 - bit data word will then be serially clocked out. the internal address word counter will then automatically increase by one. for current address read the micro - controller will not issu e an acknowledge signal o n the 18 th clock cycle. the micro - controller issues a valid stop bit after the 18 th clock cycle to terminate the read operation. the device then returns to standby mode (see figure 5). (b) s equential r ead the sequential read is very similar to current address read. the micro - controller issues a start bit and a valid device address word with read/write bit (8 th ) set to 1. the eeprom will response with an acknowledge signal on the 9 th serial clock cycle. an 8 - bit data word will then be serially clocked out. m eanwhile the internally address word counter will then automatically increase by one. unlike current address read, the micro - controller sends an acknowledge signal on the 18 th clock cycle signaling the eeprom device that it wants another byte of data. upon receiving the
ace24 a c 32 d two - wire serial eeprom ver 1. 2 7 acknowledge signal, the eeprom will serially clocked out an 8 - bit data word based on the incremented internal address counter. if the micro - controller needs another data, it sends out an acknowledge signal on the 27 th clock cycle. another 8 - bit data word will then be serially clocked out. this sequential read continues as long as the micro - controller sends an acknowledge signal after receiving a new data word. when the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. similar to current address read, the micro - controller can terminate the sequential read by not acknowledging the last data word received, but sending a stop bit afterwards instead (figure 6). (c) r andom r ead rando m read is a two - steps process. the first step is to initialize the internal address counter with a target read address using a dummy write instruction. the second step is a current address read. to initialize the internal address counter with a target r ead address, the micro - controller issues a start bit first, follows by a valid device address with the read/write bit (8 th ) set to 0. the eeprom will then acknowledge. the micro - controller will then send two address words. again the eeprom will acknowl edge. instead of sending a valid written data to the eeprom, the micro - controller performs a current address read instruction to read the data. note that once a start bit is issued, the eeprom will reset the internal programming process and continue to exe cute the new instruction - which is to read the current address (figure 7). figure 3: byte write figure 4: page write
ace24 a c 32 d two - wire serial eeprom ver 1. 2 8 figure 5: current address read figure 6: sequential read figure 7: random read notes: 1) * = dont care bits 2) # = dont care bits for ace24ac32d figure 8: scl and sda bus timing
ace24 a c 32 d two - wire serial eeprom ver 1. 2 9 ac characteristics symbol parameter 1.8v 2.5v ~ 5.0 v units min max min max f scl clock frequency, scl 400 800 khz t low clock pulse width low 1.2 0.9 s t high clock p ulse width high 0.4 0.3 s t i noise suppression time (1) 180 120 ns t aa clock low to data out valid 1.2 0.9 s t buf time the bus must be free before a new transmission can start (1) 1.3 1.2 s t hd.sta start hold time 0.6 0.6 s t su.sta start s etup time 0.6 0.6 s t hd.dat data in hold time 0 0 s t su.dat data in setup time 100 100 ns t r inputs rise time (1) 0.3 0.3 s t f inputs fall time (1) 300 300 ns t su.sto stop setup time 0.6 0.6 s t dh data out hold time 200 50 ns t wr wri te cycle time 5 5 ms endurance (1) 25 , page mode, 3.3v 1,000,000 write cycles notes: 1. this parameter is expected by characterization but are not fully screened by test. 2. ac measurement conditions: r l (connects to vcc): 1.3k input pulse voltages: 0 .3vcc to 0.7v cc input and output timin g reference voltages: 0.5 v cc
ace24 a c 32 d two - wire serial eeprom ver 1. 2 10 d c characteristics symbol parameter test condition min typ max units v cc 1 24 ac32 d supply v cc 1.8 5.5 v i cc supply r ead current v cc @5.0v scl= 4 00 khz 0.4 1.0 ma i cc supply w rite current v cc @5.0v scl= 4 00 khz 2.0 3.0 ma i sb 1 supply current v cc @1.8v, v in = v cc or v ss 0.02 1.0 a i sb 2 supply current v cc @ 2.5 v, v in = v cc or v ss 1.0 a i sb 3 supply current v cc @ 5.0 v, v in = v cc or v ss 0.07 1.0 a i li input leakage current v in = v cc or v ss 3.0 a i lo output leakage current v in = v cc or v ss 3.0 a v il input low level - 0. 6 v cc * 0.3 v v ih input high level v cc * 0.7 v cc +0. 5 v v ol 2 output low level v cc @ 3.0v, i ol = 2.1 ma 0.4 v v ol 1 output low level v cc @ 1.8 v, i ol = 0.15 ma 0. 2 v
ace24 a c 32 d two - wire serial eeprom ver 1. 2 11 packaging information dip - 8 symbol dimensions in millimeters dimensions in inches min max min max a 3.710 4.310 0.146 0.170 a1 0.510 0.020 a2 3.200 3.600 0.126 0.142 b 0.380 0.570 0.015 0.022 b1 1.524 bsc 0.060 bsc c 0.204 0.360 0.008 0.014 d 9.000 9.400 0.354 0.370 e 6.200 6.600 0.244 0.260 e1 7.320 7.920 0.288 0.312 e 2.540 (bsc) 0.100 bsc l 3.000 3.600 0.118 0.142 e2 8.400 9.000 0.331 0.354
ace24 a c 32 d two - wire serial eeprom ver 1. 2 12 packaging informati on sop - 8 symbol dimensions in millimeters dimensions in inches min max min max a 1.350 1.750 0.053 0.069 a1 0.100 0.250 0.004 0.010 a2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 d 4.700 5.100 0.185 0.200 e 3.800 4.000 0.150 0.157 e1 5.800 6.200 0.228 0.244 e 1.270 (bsc) 0.050 (bsc) l 0.400 1.270 0.016 0.050 0 8 0 8
ace24 a c 32 d two - wire serial eeprom ver 1. 2 13 packaging information m sop - 8 symbol dimensions in millimeters dimensions in inches min max min max a 0.820 1.100 0.320 0.043 a1 0.020 0.150 0.001 0 .006 a2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 d 2.900 3.100 0.114 0.122 e 0.65 (bsc) 0.026 (bsc) e 2.900 3.100 0.114 0.122 e1 4.750 5.050 0.187 0.199 l 0.400 0.800 0.016 0.031 0 6 0 6
ace24 a c 32 d two - wire serial eeprom ver 1. 2 14 packaging information ts sop - 8 symbol dimensions in millimeters dimensions in inches min max min max d 2.900 3.100 0.114 0.122 e 4.300 4.500 0.169 0.177 b 0.190 0.3 00 0.007 0.012 c 0.090 0.200 0.004 0.008 e1 6.250 6.550 0.246 0.258 a 1.100 0.043 a2 0.800 1.000 0.031 0.039 a1 0.020 0.150 0.001 0.006 e 0.65 (bsc) 0.026 (bsc) l 0.500 0.700 0.020 0.028 h 0.25 (typ) 0.01 (typ) 1 7 1 7
ace24 a c 32 d two - wire serial eeprom ver 1. 2 15 packaging information u son3*2 - 8 symbol dimensions in millimeters dimensions in inches min max min max a 0.450 0.550 0.017 0.021 a1 0.000 0.050 0.000 0.002 b 0.180 0.300 0.007 0.039 b1 0.160ref 0.006r ef c 0.100 0.200 0.004 0.008 d 1.900 2.100 0.075 0.083 d2 1.400 1.600 0.055 0.062 e 0.500bsc 0.020bsc nd 1.500bsc 0.059bsc e 2.900 3.100 0.114 0.122 e2 1.500 1.700 0.059 0.067 l 0.300 0.500 0.012 0.020 h 0.200 0.300 0.066 0.12
ace24 a c 32 d two - wire serial eeprom ver 1. 2 16 packaging information sot - 23 - 5 symbol dimensions in millimeters dimensions in inches min max min max a 1.050 1.250 0.041 0.049 a1 0.000 0.100 0.000 0.004 a2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0. 004 0.008 d 2.820 3.020 0.111 0.119 e 1.500 1.700 0.059 0.067 e1 2.650 2.950 0.104 0.116 e 0.95 (bsc) 0.037 (bsc) e1 1.800 2.000 0.071 0.079 l 0.300 0.600 0.012 0.024 0 8 0 6
ace24 a c 32 d two - wire serial eeprom ver 1. 2 17 packaging information tsot - 23 - 5 symbol dimensions in millimeters dimensions in inches min max min max a 0.700 0.900 0.028 0.035 a1 0.000 0.100 0.000 0.004 a2 0.700 0.800 0.028 0.031 b 0.350 0.500 0.014 0.020 c 0.080 0.200 0.003 0.008 d 2.820 3.020 0.111 0.119 e 1.600 1 .700 0.063 0.067 e1 2.650 2.950 0.104 0.116 e 0.95 (bsc) 0.037 (bsc) e1 1.90 (bsc) 0.075 (bsc) l 0.300 0.600 0.012 0.024 0 8 0 6
ace24 a c 32 d two - wire serial eeprom ver 1. 2 18 notes ace does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ace elect ronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructi ons for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failur e of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace - ele.com/


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